MULTIPLIERLESS IIR FILTER DESIGN FOR FPGA
Keywords:
VHDL, FPGA, IIR filter, allpass filterAbstract
The paper deals with a method of IIR filter design, in which the coefficients in the canonical binary number system representation are searched using the simulated annealing algorithm. The IIR filters are designed on the base of the all-pass filter stages, masking filters and multiplied delays in them. The filter coefficients are selected which have no more than three summands in their representation. Therefore, its pipelined implementation in FPGA has the highest clock frequency and minimum hardware volume. The use of the VHDL language in all the steps of the filter design helps to speed-up and improve the filter optimization.
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