MINIMIZED HARDWARE FIR FILTER DESIGN

Authors

  • Sergiyenko Anatoliy National Technical University of Ukraine "Igor Sikorsky Kyiv Polytechnic Institute", Ukraine
  • Mustafa Rekar Quasim National Technical University of Ukraine "Igor Sikorsky Kyiv Polytechnic Institute", Ukraine
  • Anastasia Anatoliivna Serhienko National Technical University of Ukraine "Igor Sikorsky Kyiv Polytechnic Institute", Ukraine

Abstract

The development of the parallel finite impulse response filters for the FPGA implementation is considered. A new method consists in substituting the multipliers to the small coefficients to the constant coefficient multipliers, which store the multiplied values of these coefficients. Due to this, the filter hardware volume is minimized and its throughput is increased. 

Key words: FPGA, FIR filter, pipeline. 

Fig.: 3. Tabl.:1. Bibl.: 4.

Published

2023-11-08

Issue

2018

Section

IoT, Real Time Systems