ANALYSIS OF EFFICIENCY OF ADDITION OPERATION REALIZATION IN ON-LINE MODE

Abstract

The article deals with an algorithm and hardware implementation of two-place and multi-place functions of addition in on-line mode, which allows to combine the processes of bit-by-bit input, processing and bit-by-bit output of information, starting with the high-order bit with the use of redundant number system. It is shown that the implementation of a multi-place function enables to reduce delay in the result digit obtaining, as well as scope of equipment.

Key words: on-line computations, redundant number system, dependent operations overlap.

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