METHOD OF SIMPLIFICATION OF COMPUTATIONS WITH A FLOATING POINT IN THE SUPERSCALAR PROCESSOR

Authors

  • Heorhii Loutskii Department of Computer Engineering, National Technical University of Ukraine “Igor Sikorsky Kyiv Polytechnic Institute”, Ukraine https://orcid.org/0000-0002-3155-8301
  • Andrii Dolgolenko National Technical University of Ukraine “Igor Sikorsky Kyiv Polytechnic Institute", Ukraine
  • Oleksandr Dolgolenko Department of Computer Engineering, National Technical University of Ukraine “Igor Sikorsky Kyiv Polytechnic Institute”, Ukraine

Keywords:

Operational Device, RISC Operations, Floating-Point, Law of Associativity, Kahan's Algorithm

Abstract

This article describes results of development of the approach to building fast operational device of adding-subtracting a long sequence of floating-point numbers with dynamic branching of work at the level of RISCs, which without additional software complications, will ensure the law of associativity when performing addition of sequence of positive numbers. This paper describes the functional circuit of such operational device which does not require for its work elements of firmware control. The operational device can be implemented for SF and F formats of floating-point numbers. For other formats such implementation of the operational device is more reasonable to base on an algorithm similar to the Kahan 's algorithm.

References

Y. Patt, W. Hwu, et al, Experiments with HPS, a Restricted Data Flow Micro architecture for High Performance Computers, Digest of Papers, COMPCON 86, (March 1986), pp. 254-258.

M. Simone, A. Essen, A. Ike, A. Krishnamoorthy, T. Maruyama, N. Patkar, M. Ramaswami, M. Shebanow, V. Thirumalaiswamy, D. Tovey (1995). Implementation trade-offs in using a restricted data flow architecture in a high performance RISC microprocessor. New York. pp. 151-162.

John L. Hennessy, David A. Patterson. Computer Architecture. A Cuantitative Approach, USA, Morgan Kaufmann, 2012 – 497 p.+ add-ins.

Kanter, David (November 13, 2012). "Intel’s Haswell CPU Microarchitecture" (http://www.realworldtech.com/ haswell-cpu/).

J.Shen, M. Lipasti. Modern Processor Design: Fundamentals of Superscalar Processors. Waveland Press, 2013- 642 p.

IEEE 754: Standard for Binary Floating-Point Arithmetic / 3 april 2014. – URL: http://grouper.ieee.org/groups/754/.

What Every Computer Scientist Should Know About Floating-Point Arithmetic. – URL: https://ece.uwaterloo.ca/~dwharder/NumericalAnalysis/ 02Numerics/Double/paper.pdf.

Higham, Nicholas J. Accuracy and Stability of Numerical Algorithms. SIAM, 2002, pp. 110–123.

Downloads

Published

2023-06-04

Issue

2019

Section

IoT, Real Time Systems