METHOD OF MAPPING CYCLO-DYNAMIC DATA FLOWS INTO HARDWARE
Keywords:
data flow graph, field programable gate array, VHDL, pipeline, dynamic scheduleAbstract
The article focuses on the relevance of high-level synthesis (HLS) systems used for designing pipelined datapaths. The goal is to explore methods of mapping algorithms to the pipelined datapaths implementing the cyclic data flow graphs with dynamic schedules. The proposed method involves creating and optimizing cyclo-dynamic data flow graphs, describing them in VHDL. The method demonstrates its effectiveness through examples like run-length encoding decompression and can be implemented in HLS tools.
References
Gajski D. D., Abdi S., Gerstlauer A., Schirner G. (2009). Embedded System Design. Modeling, Synthesis and Verification. Springer. 352 p.
Schaumont P. (2011). A Practical Introduction to Hardware/Software Codesign. Springer. 396 p.
Lee E. A., Messerschmitt D. G. (1987). Synchronous data flow. in Proceedings of the IEEE, vol. 75, no. 9, pp. 1235-1245, Sept. 1987, doi: 10.1109/PROC.1987.13876.
Lee E. A, Neuendorffer S. (2005). Concurrent models of computation for embedded software. IEE-INST ELEC ENG. IEE Proceedings Computers and Digital Techniques, Vol. 152. No. 2, pp. 239-250.
Khan S. A. (2011). Digital Design of Signal Processing Systems. A Practical Approach. UK: Wiley.
Sergiyenko A., Serhienko A., Simonenko A. (2017). A method for synchronous dataflow retiming. 2017 IEEE First Ukraine Conference on Electrical and Computer Engineering (UKRCON), Kyiv, Ukraine, april 2017, pp. 1015-1018, doi: 10.1109/UKRCON.2017.8100404.
Parks T. M., Pino J. L., Lee E. A. (1995). A comparison of synchronous and cycle-static dataflow. Conference Record of The Twenty-Ninth Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, USA, pp. 204-210 vol.1, doi: 10.1109/ACSSC.1995.540541.
Bhattacharya B., Bhattacharyya S. (2001). Parameterized dataflow modeling for DSP systems. IEEE Transactions on Signal Processing. V. 49. No. 10, pp. 2408–2421.
Wauters P., Engels M., Lauwereins R., Peperstraete J. A. (1996). Cyclodynamic dataflow. Proceedings of 4th Euromicro Workshop on Parallel and Distributed Processing, Braga, Portugal, 1996, pp. 319-326, doi: 10.1109/EMPDP.1996.500603.
Fradet P., Girault A., Poplavko P. (2012). SPDF: A schedulable parametric data-flow MoC. Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, 2012, pp. 769-774, doi: 10.1109/DATE.2012.6176572.
Сергиенко А. М. (2004). VHDL для проектирования вычислительных устройств. Киев: Диасофт. 205 с.
Woods R., McAllister J., Lightbody G., Yi Y. FPGA-based Implementation of Signal Processing Systems. Wiley, 2d Ed. 2017, 447 p.
